The present disclosure relates to a solid-state imaging apparatus, a method of manufacturing the solid-state imaging apparatus, and an electronic apparatus.
Hitherto, examples of solid-state imaging apparatuses used for digital cameras, video cameras, and the like include CCD-type solid-state imaging apparatuses and CMOS-type solid-state imaging apparatuses. In these solid-state imaging apparatuses, a light-receiving unit is formed for each of a plurality of pixels that are formed in a two-dimensional matrix, and in this light-receiving unit, signal electric charge is generated in correspondence with the amount of received light. Then, the signal electric charge generated in the light-receiving unit is transferred and amplified, thereby obtaining an image signal.
In solid-state imaging apparatuses, in order that processing variations at the time of the formation of photodiodes are reduced so as to prevent transfer efficiency resulting from the processing variations from being reduced, a method in which photodiodes are formed by self-alignment is adopted. In addition, in order to improve transfer efficiency, in the disclosures described in Japanese Unexamined Patent Application Publication Nos. 11-126893 and 2008-66480, and Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2009-518850, a method has been proposed in which an electric charge storage area forming a photodiode is formed so as to be superposed directly below the transfer gate electrode.
Furthermore, in photodiodes, in order for dark current to be suppressed, it is common practice to form a semiconductor area of a conductive type opposite to that of an electric charge storage layer on the surface of a semiconductor substrate. In order to increase the pinning effect in a semiconductor area for suppressing dark current, in the disclosure described in Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2009-518850, a configuration in which a semiconductor area (for example, p-type semiconductor area) for pinning is superposed directly below a transfer gate electrode has been proposed.
The configuration in which the electric charge storage layer and the semiconductor area for suppressing dark current are arranged so as to overlap the transfer gate electrode has advantages and disadvantages. Depending on the case, it may be difficult to implement configurations that satisfy all of the formation of photodiodes, securing of pinning below a transfer gate electrode, and securing of a transfer margin. For example, a dopant that is implanted for securing pinning acts in a direction that obstructs the transfer of signal electric charge, and a dopant that is ion-implanted for securing a transfer margin acts in a direction that weakens pinning below a transfer gate electrode.
As described above, in the configuration of the solid-state imaging apparatus of the related art, there is a trade-off relationship between securing of pinning for dark current suppression and securing of a transfer margin, and design of this area around a transfer gate electrode is difficult.